1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, it relates to a semiconductor memory device comprising data read means reading data stored in storage means.
2. Description of the Background Art
A semiconductor memory device comprising data read means for reading data stored in storage means is known in general. FIG. 5 shows the structure of a one-transistor one-capacitor (1T1C) ferroelectric memory comprising a comparator (data read means) as an exemplary semiconductor memory device comprising data read means. The ferroelectric memory is a nonvolatile memory utilizing pseudo capacitance variation responsive to the direction of polarization of a ferroelectric substance as a memory element. As shown in FIG. 5, this 1T1C ferroelectric memory comprises a memory cell (storage means) 101 connected between a word line WL and a plate line PL and between the plate line PL and a bit line BL and a comparator 102 connected to the bit line BL. The memory cell 101 includes a ferroelectric capacitor 103 and a selection transistor 107. The word line WL is connected to the gate of the selection transistor 107. The comparator 102 is supplied with a reference potential Vref generated by a prescribed method.
In a read operation, the conventional 1T1C ferroelectric memory shown in FIG. 5 activates the word line WL, thereby turning on the selection transistor 107. Thereafter the ferroelectric memory applies a prescribed read potential to the plate line PL. Thus, a potential responsive to data “1” or “0” stored in the memory cell 101 appears on the bit line BL. Thereafter the ferroelectric memory generates an intermediate potential between those corresponding to the data “1” and “0” respectively by the prescribed method and supplies this potential to the comparator 102. The ferroelectric memory employs the potential generated by the prescribed method as the reference potential Vref and compares the potential corresponding to the data of the memory cell 101 appearing on the bit line BL with the reference potential Vref through the comparator 102, thereby determining the data read from the memory cell 101 as “0” or “1”. The ferroelectric memory outputs the data “1” or “0” of the memory cell 101 determined as “0” or “1” from the comparator 102.
FIG. 6 shows a one-capacitor (1C) cross-point ferroelectric memory comprising a comparator (data read means) 112 as another exemplary conventional semiconductor memory device comprising data read means. As shown in FIG. 6, the 1C cross-point ferroelectric memory comprises a word line WL, a bit line BL, a memory cell 111 connected to the word line WL and the bit line BL and the comparator 112 connected to the bit line BL. The memory cell 111 is constituted of only a ferroelectric capacitor 113 consisting of the word line WL, the bit line BL and a ferroelectric film (not shown) arranged between the word line WL and the bit line BL. The comparator 112 is supplied with a reference potential Vref generated by a prescribed method.
In a read operation, the conventional 1C cross-point ferroelectric memory shown in FIG. 6 applies a read potential to the word line WL. Thus, a potential responsive to data “1” or “0” stored in the memory cell 111 appears on the bit line BL. At this time, the ferroelectric memory generates the reference potential Vref at an intermediate level between potentials corresponding to the data “1” and “0” respectively by the prescribed method and supplies the same to the comparator 112. Similarly to the aforementioned 1T1C ferroelectric memory, the 1C cross-point ferroelectric memory compares the potential corresponding to the data read from the memory cell 111 on the bit line BL with the reference potential Vref through the comparator 112, thereby determining the data “0” or “1” and outputting the same from the comparator 112.
However, the conventional 1T1C ferroelectric memory shown in FIG. 5 utilizing the reference potential Vref for determining the data “0” or “1” read on the bit line BL must be provided with a circuit for generating the reference potential Vref. Thus, the size of the ferroelectric memory is disadvantageously increased.
The 1C cross-point ferroelectric memory shown in FIG. 6, also employing the reference potential Vref for determining the data “0” or “1” read from the memory cell 111 on the bit line BL, is also disadvantageously increased in size similarly to the conventional 1T1C ferroelectric memory shown in FIG. 5.
Therefore, a semiconductor memory device capable of determining data without a reference potential is proposed in general. For example, “A 512 Kb Cross-Point Cell MRAM”, ISSCC 2003/SESSION 16/NON-VOLATILE MEMORY/PAPER 16.1, for example, proposes such a semiconductor memory device.
The aforementioned literature “A 512 Kb Cross-Point Cell MRAM”, ISSCC 2003/SESSION 16/NON-VOLATILE MEMORY/PAPER 16.1 discloses a cross-point MRAM (magnetic random access memory) constituted to perform self-comparative reading requiring no reference potential in a read operation. More specifically, the aforementioned cross-point MRAM performs first data reading from a memory cell while holding a voltage corresponding to the read data. Then, the MRAM writes data “0” or “1” in the memory cell. Then, the MRAM performs second data reading from the memory cell while comparing the held voltage corresponding to the data read through the first data reading with a voltage corresponding to the data “0” or “1” read through the second data reading, thereby determining the data read through the first data reading. The cross-point MRAM disclosed in the aforementioned literature “A 512 Kb Cross-Point Cell MRAM”, ISSCC 2003/SESSION 16/NON-VOLATILE MEMORY/PAPER 16.1 may not employ a reference potential due to the self-comparative reading.
However, the cross-point MRAM proposed in the aforementioned literature “A 512 Kb Cross-Point Cell MRAM”, ISSCC 2003/SESSION 16/NON-VOLATILE MEMORY/PAPER 16.1 requires three cycles of operations, i.e., the first read operation, the operation of writing the data “0” or “1” and the second read operation, in order to read the data from the memory cell and determine the same. Thus, the operating time of the cross-point MRAM is disadvantageously increased due to the large number of operations.